1. Field of the Invention
The present invention relates generally to graphics processing and, more specifically, to memory coherency in graphics command streams and shaders.
2. Description of the Related Art
Shaders may perform random-access read and write operations to texture or buffer object memory locations through built-in image load, store, and atomic operations. However, the ability to perform such random-access read and write operations in a system that is highly pipelined and performs many operations concurrently results in graphics command stream execution order and synchronization inaccuracies, as the order in which texture or buffer object memory locations are read from or written to by one or more shaders is largely undefined.
For example, in a system that processes multiple primitives in parallel, a store operation issued by a shader when working on a first primitive might complete after a store operation for a second primitive, even if the first primitive was specified prior to the second primitive. This is problematic when the second primitive is dependent upon the first primitive. Further, the limitations on the order of thread launch and execution make some forms of cross-thread synchronization within a single set of primitives impossible. For example, having one thread poll a memory location written by another thread assumes that the other thread has already launched, performed a modification to the memory location, and ceased in execution—which is often not the case. Further, in systems with a parallel memory subsystem, transactions to different memory locations may be spread across multiple load/store units to maximize throughput. However, this behavior means that stores issued to different memory locations within a single shader invocation may not be visible to other threads in the order in which they were requested to execute.
As the foregoing illustrates, what is needed in the art is a mechanism for ensuring the coherency of memory read and write operations in a highly-pipelined system.